1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a semiconductor memory device with a test mode.
2. Description of the Background Art
FIG. 7 is a plan view of a layout of a chip for a conventional dynamic random access memory (referred to as a DRAM hereinafter).
Referring to FIG. 7, the DRAM includes four memory mats 10 each provided at one of four corners of the memory chip, a row decoder 11 and a column decoder 12 provided for each memory mat 10, and a peripheral circuit region 13 provided at the center of the memory chip. Each memory mat 10 includes a plurality of memory arrays MA1-MA16 and a plurality of sense amplifier bands SA1-SA17 arranged along the direction of the longer side of the chip. Each of memory arrays MA1-MA16 and each of sense amplifier bands SA1-SA17 are alternately arranged.
Each of memory arrays MA1-MA16 includes a plurality of memory cells each for storing data of one bit. Each memory cell is arranged at a predetermined address which is determined according to row and column addresses.
Row decoder 11 is responsive to a row address signal for selecting any of memory arrays MA1-MA16 and designating any row address of the selected memory array. Column decoder 12 is responsive to a column address signal for designating any column address of memory arrays MA1-MA16.
Arranged in sense amplifier bands SA1-SA17 is a circuit for inputting/outputting data between the memory cell of the address designated by row and column decoders 11 and 12 and the outside. A circuit for controlling the entire DRAM, a power supply circuit and the like are arranged in peripheral circuitry region 13.
FIG. 8 shows in detail a configuration of the memory array MA1 and sense amplifier bands SA1 and SA2 shown in FIG. 7.
Referring to FIG. 8, memory array MA1 is configured in the so-called half-pitch cell arrangement, and includes a plurality (16 in the figure) of bit lines BL and /BL, and a pair MCP of memory cells periodically arranged at the intersection of two word lines WL and one bit line BL or /BL. Sense amplifier bands SA1 and SA2 are each provided with a plurality (four in the figure) of sense amplifier+input/output control circuits 15.
The pair MCP of memory cells includes a memory cell MC connected to one word line WL of two word lines WL and to bit line BL, and a memory cell MC connected to the other word line WL and to bit line BL, as shown in FIG. 9A. Memory cell MC includes an n-channel MOS transistor 20 for access and a capacitor 21 for storing information.
The pair MCP of memory cells is practically formed on a surface of a p silicon substrate 22, as shown in FIG. 9B. A gate electrode or word line WL is formed on a surface of p silicon substrate 22 with a gate oxide film (not shown) interposed therebetween and n.sup.+ source/drain regions 23a, 23b and 23c are formed in the surface of silicon substrate 22 at one side of each of two word lines WL as well as between the two word lines WL to form two n-channel MOS transistors 20. The common source/drain region 23c of the two n-channel MOS transistors 20 is connected to bit line BL, and a conductive layer 24, a dielectric layer 25 and a conductive layer 26 are deposited on the surface of each of source/drain regions 23a and 23b to form capacitor 21 of memory cell MC. Conductive layer 24 serves as one electrode of capacitor 21 or a storage node SN, and conductive layer 26 serves as the other electrode of capacitor 21 to receive a cell potential Vcp.
An odd-numbered bit line BL and even-numbered bit line /BL which are arranged adjacent to each other form a pair of bit lines BL and /BL. A pair MCP of memory cells is arranged at the intersection of an odd-numbered bit line BL and (4m+1)th and (4m+2)th word lines WL, wherein m represents an integer equal to or larger than zero. A pair MCP of memory cells is arranged at the intersection of an even-numbered bit lines /BL and (4m+3)th and (4m+4)th word lines WL.
Pairs of bit lines BL and /BL configured of a (4n+1)th bit line and a (4n+2)th bit line are connected to their respective sense amplifier+input/output control circuits 15 in sense amplifier band SA1, wherein n represents an integer equal to or larger than zero. Pairs of bit lines BL and /BL configured of a (4n+3)th bit line and a (4n+4)th bit line are connected to their respective sense amplifier+input/output control circuits 15 in sense amplifier band SA2. Each sense amplifier+input/output control circuit 15 in sense amplifier bands SA1 and SA2 receives a precharge potential VBL (=Vcc/2).
Sense amplifier+input/output control circuit 15 in sense amplifier band SA2 includes transfer gates 30 and 34, a column select gate 31, a sense amplifier 32 and an equalizer 33, as shown in FIG. 10.
Transfer gate 30 includes n-channel MOS transistors 41 and 42. N-channel MOS transistors 41 and 42 are connected between input/output nodes N1 and N2 of sense amplifier+input/output control circuit 15 and a corresponding pair of bit lines BL and /BL of memory array MA2, respectively, and the gates of n-channel MOS transistors 41 and 42 receive a memory array select signal BLIR.
Transfer gate 34 includes n-channel MOS transistors 52 and 53. N-channel MOS transistors 52 and 53 are connected between input/output nodes N1 and N2 and a corresponding pair of bit lines BL and /BL of memory array MA1, respectively, and the gates of n-channel MOS transistors 52 and 53 receive a memory array select signal BLIL. Sense amplifier+input/output control circuit 15 in sense amplifier band SA2 is shared by two memory arrays MA1 and MA2 arranged on the both sides of the sense amplifier+input/output control circuit 15. When memory array MA1 is selected, signal BLIR attains a low level and transfer gate 30 is shut down. When memory array MA2 is selected, signal BLIL attains a low level and transfer gate 34 is shut down.
Column select gate 31 includes n-channel MOS transistors 43 and 44 connected between input/output nodes N1 and N2 and signal input/output lines IO and /IO, respectively. The gates of n-channel MOS transistors 43 and 44 are connected to column decoder 12 via a column select line CSL. When column decoder 12 causes column select line CSL to rise to a high level as the selected level, n-channel MOS transistors 43 and 44 are turned on and input/output nodes N1 and N2, that is, the pair of bit lines BL and /BL of memory array MA1 or MA2 are coupled with the pair of data signal input/output lines IO and /IO.
Sense amplifier 32 includes p-channel MOS transistors 45 and 46 connected between input/output nodes N1 and N2 and a node N3, respectively, and also includes n-channel MOS transistors 47 and 48 connected between input/output nodes N1 and N2 and a node N4, respectively. The gates of MOS transistors 45 and 47 are both connected to node N2, and the gates of MOS transistors 46 and 48 are both connected to node N1. Nodes N3 and N4 receive sense amplifier activating signals SE and /SE, respectively. When sense amplifier activating signals SE and /SE attain a high level and a low level, respectively, sense amplifier 32 responsively amplifies a slight, potential difference between nodes N1 and N2, i.e., between paired bit lines BL and /BL of memory array MA1 or MA2 to the power supply voltage Vcc.
Equalizer 33 includes an n-channel MOS transistor 49 connected between input/output nodes N1 and N2, and n-channel MOS transistors 50 and 51 connected between input/output nodes N1 and N2 and a node N6, respectively. The gates of n-channel MOS transistors 49-51 are all connected to node N5. Node N5 receives a bit line equalization signal BLEQ, and node N6 receives precharge potential VBL (=Vcc/2). When bit line equalization signal BLEQ attains an active high level, equalizer 33 responsively equalizes the potentials of nodes N1 and N2, i.e., the potentials of bit lines BL and /BL of memory array MA1 or MA2 with precharge potential VBL. It should be noted that signals BLIR, BLIL, SE, ISE and BLEQ and precharge potential VBL are provided from a circuit in peripheral circuitry region 13 shown in FIG. 7.
The other memory arrays MA2-MA16 and sense amplifier bands SA3-SA17 also have the same structure.
An operation of the DRAM shown in FIGS. 7-10 will now be described briefly. On standby, signals BLIR, BLIL and BLEQ all attain a high level, signals SE and /SE both attain an intermediate level (Vcc/2), and the potentials of bit lines BL and /BL are equalized with precharge potential VBL. Word line WL and column select line CSL each attain a low level as the non-selected level.
In the write mode, bit line equalization signal BLEQ initially falls to a low level to stop the equalization between bit lines BL and /BL. Then, in response to a row address signal, row decoder 11 selects, for example, memory array MA1 and sets signals BLIR and BLIL to low and high levels, respectively, to couple memory array MA1 with sense amplifier bands SA1 and SA2. Furthermore, row decoder 11 causes the word line WL of the row corresponding to the row address signal to rise to a high level as the selected level and turn on n-channel MOS transistors 20 of memory cells MC of the row.
Then, column decoder 12 causes column select line CSL for the column corresponding to a column address signal to rise to an active high level and turn on column select gate 31. Write data externally applied is provided to the pair of bit lines BL and /BL of the selected column via the pair of data input/output lines IO and /IO. The write data is provided as a potential difference between bit lines BL and /BL. Capacitor 21 of the selected memory cell MC stores therein the amount of an electrical charge corresponding to the potential of bit line BL or /BL.
In the read mode, bit line equalization signal BLEQ initially falls to a low level and the equalization between bit lines BL and /BL is stopped. As is in the write mode, row decoder 21 selects, for example, memory array MA1 and couples memory array MA1 with sense amplifier bands SA1 and SA2 as well as causes the word line WL of the row corresponding to a row address signal to rise to a high level as the selected level. The potentials of bit lines BL and /BL slightly change depending on the amount of electrical charge stored in capacitor 21 of the activated memory cell MC.
Then, sense amplifier activating signals SE and /SE attain high and low levels, respectively, to activate sense amplifier 32. When the potential of bit line BL is slightly higher than that of bit line /BL, the resistance values of MOS transistors 45 and 48 are smaller than those of MOS transistors 46 and 47, respectively, and the potential of bit line BL is increased to high level and the potential of bit line /BL is reduced to low level. When the potential of bit line /BL is slightly higher than that of bit line BL, the resistance values of MOS transistors 46 and 47 are smaller than those of MOS transistors 45 and 48, respectively, and the potential of bit lines /BL is increased to high level and the potential of bit line BL is reduced to low level.
Then, column decoder 12 causes column select line CSL of the column corresponding to a column address signal to rise to a high level as the selected level to turn on column select gate 31 of the column. The data on the pair of bit lines BL and /BL of the selected column is externally output via column select gate 31 and the pair of data signal input/output lines IO and /IO.
FIG. 11 shows the main portion of another conventional DRAM in comparison with that shown in FIG. 8. The DRAM shown in FIG. 11 is configured in a so-called quarter-pitch cell arrangement.
More specifically, (4n+1)th and (4n+3)th bit lines configure a pair of bit lines BL and /BL, and (4n+2)th and (4n+4)th bit lines configure a pair of bit lines BL and /BL. A pair MCP of memory cells is arranged at the intersection of a (4n+1)th bit line and (4m+1)th and (4m+2)th word lines. A pair MCP of memory cells is arranged at the intersection of a (4n+2)th bit line and (4m+2)th and (4m+3)th word lines. A pair MCP of memory cells is arranged at the intersection of a (4n+3)th bit line and (4m+3)th and (4m+4)th word lines. A pair MCP of memory cells is arranged at the intersection of a (4n+4)th bit line and (4m+4)th and (4m+5)th word lines.
Each odd-numbered pair of bit lines BL and /BL configured of (4n+1)th and (4n+3)th bit lines is connected to sense amplifier+input/output control circuit 15 in sense amplifier band SA1. Each even-numbered pair of bit lines BL and /BL configured of (4n+2)th and (4n+4)th bit lines is connected to sense amplifier+input/output control circuit 15 in sense amplifier band SA2.
The rest of the configuration and operation of the DRAM is the same as the DRAM shown in FIGS. 7-10 and thus a description thereof is not repeated.
Quarter-pitch cell arrangement is more advantageous than half-pitch cell arrangement in that laterally elongate capacitor 21 of memory cell MC can be rotated by 90.degree. and arranged as a longitudinally elongate capacitor, as shown in FIG. 12.
In order to ensure the reliability of such a DRAM, conventionally, dynamic burn-in testing has been generally conducted by dynamically operating each chip for a long period of time (normally, several tens of hours) under a temperature and voltage stress condition higher than the normal operating condition to accelerate generation of initial failures for screening any chips with the possibility of causing initial failures in the market and thus preventing the shipment of such chips to the market.
In conventional burn-in testing, one word line WL and one column select line CSL represented by thick solid lines are selected by row decoder 11 and column decoder 12 to select one memory cell MC indicated by a circle, as shown in FIG. 13. In this burn-in testing, while electric field stress is applied between a word line WL selected by row decoder 11 a nd a word line WL adjacent thereto, the acceleration effect is small, since word lines WLs are selected one by one.
Thus, a method has been proposed which enhances acceleration effect by selecting odd-numbered word lines WL1, WL3, . . . or even-numbered word lines WL2, WL4, . . . at one time. FIGS. 14 and 15 are block circuit diagrams showing main portions of a DRAM capable of implementing such a testing method.
Referring to FIGS. 14 and 15, row decoder 11 of the DRAM includes word drivers WD1, WD2, . . . provided for word lines WL1, WL2, . . . , respectively. Each of word drivers WD1, WD2, . . . is configured of an inverter which inverts, amplifies and provides internal signals V1, V2, . . . on word lines WL1, WL2, . . . , respectively.
More specifically, odd-numbered word drivers WD1, WD3 . . . each include a p-channel MOS transistor 61 and an n-channel MOS transistor 62. P-channel MOS transistor 61 is connected between a line for a power supply potential Vcc and a corresponding word line (e.g., WL1), and has its gate receiving a corresponding internal signal (e.g., V1). N-channel MOS transistor 62 is connected between a line for a power supply potential VA and a corresponding word line (WL1 in this example), and has its gate receiving a corresponding internal signal (V1 in this example).
Even-numbered word drivers WD2, WD4, . . . each include a p-channel MOS transistor 63 and an n-channel MOS transistor 64. P-channel MOS transistor 63 is connected between a line for power supply potential Vcc and a corresponding word line (e.g., WL2), and has its gate receiving a corresponding internal signal (e.g., B2). N-channel MOS transistor 64 is connected between a line for a power supply potential VB and a corresponding word line (WL2 in this example), and has its gate receiving a corresponding internal signal (V2 in this example).
Power supply potentials VA and VB are generated in a VA generation circuit 65 and a VB generation circuit 66, respectively. When a burn-in testing signal BIl attains an active high level, VA generation circuit 65 responsively outputs a high level (power supply potential Vcc). When burn-in testing signal B11 attains an inactive low level, VA generation circuit 65 responsively outputs a low level (a ground potential GND). When a burn-in testing signal BI2 attains an active high level, VB generation circuit 66 responsively outputs a high level. When burn-in testing signal BI2 attains an inactive low level, VB generation circuit 66 outputs a low level.
An operation of the DRAM shown in FIGS. 14 and 15 will briefly be described.
As shown in FIGS. 16A-16E, at standby, burn-in test signals BI1 and BI2 both attain an inactive low level and power supply potentials VA and VB both attain ground potential GND. Furthermore, internal signals V1, V2, . . . all attain a high level and word lines WL1, WL2, . . . all attain ground potential GND.
In burn-in testing, only burn-in testing signal BI1 of burn-in testing signals BI1 and BI2 attains an active high level, and only power supply potential VA of power supply potentials VA and VB attains a high level. Thus, odd-numbered word lines WL1, WL3, . . . attain a high level and even-numbered word lines WL2, WL4, . . . attain a low level, and thus electric field stress is simultaneously applied between word lines and those adjacent thereto.
Then, only burn-in testing signal BI2 of burn-in testing signals BI1 and BI2 attains an active high level and only power supply potential VB of power supply potentials VA and VB attains a high level. Thus, even-numbered word lines WL2, WL4, . . . attain a high level and odd-numbered word lines WL1, WL3, . . . attain a low level, and thus electric field stress in the inverted direction is simultaneously applied between word lines and those adjacent thereto.
The acceleration effect of conventional burn-in testing is, however, not satisfactory.